Sharvani Gadgil
Assistant Professor
sharvani.gadgil@mahindrauniversity.edu.in
Dr. Sharvani Gadgil is an Assistant Professor in the Electrical and Electronics Engineering Department at École Centrale School of Engineering, Mahindra University. She completed her Ph.D. in the Discipline of Electrical and Electronics Engineering from Birla Institute of Technology and Science-Pilani, Hyderabad Campus, India in 2024. Prior to joining Mahindra University, she worked for ASL, a DRDO lab in Hyderabad as a Research Associate for a brief period. She has worked as an Associate Software Engineer at Robert Bosch post her B-tech for 2 years. She also has experience of working in various academic institutions such as JNTU Hyderabad, IIIT-Hyderabad and BITS-Pilani, Hyderabad campus for various research activities.
Ph.D.
- Ph.D. in VLSI Design, Birla Institute of Technology and Science (BITS)-Pilani, Hyderabad Campus
M.Tech in Embedded Systems
- M.Tech in Embedded Systems, VNR VJIT, JNTU Hyderabad
B.Tech
- B.Tech (ECE), Vardhaman College of Engineering, JNTU Hyderabad.
(2012-2014)
- Dr. Sharvani Gadgil worked as an Associate Software Engineer at Robert Bosch, Bengaluru, (2012-2014).
2018 for a period of 6 months.
- She was a Research Associate at IIIT Hyderabad in 2018 for a period of 6 months.
2019-2023
- She also worked as a Teaching Assistant and a Ph.D. scholar at BITS-Pilani, Hyderabad Campus from 2019-2023
2024 from July-Dec 2024
- She was a Research Associate at the ASL, DRDO, Hyderabad in 2024 from July-Dec 2024 for a period of 5 months.
Journals
2024
- S. Gadgil G. Naga Sandesh and C. Vudadha, “Design of a Ternary Logic Processor using CNTFET technology,” in Circuits, Systems and Signal Processing Journal, 2024 doi : 10.1007/s00034-024-02726-x
2023
- S. Gadgil and C. Vudadha, “Power efficient designs of CNTFET-based ternary SRAM,” in Microelectronics Journal, 2023, doi: 10.1016/j.mejo.2023.105884.
2022
- S.Gadgil and C. Vudadha, “Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits,” in IEEE Transactions on Nanotechnology, vol. 21, pp. 289-298, 2022, doi: 10.1109/TNANO.2022.3184759.
2020
- S.Gadgil and C. Vudadha, “Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach,” in IEEE Transactions on Nanotechnology, vol. 19, pp. 661-671, 2020, doi: 10.1109/TNANO.2020.3018867.
Conferences
2022
- S. T, S. Gadgil and C. Vudadha, “Design of CNTFET-based Ternary Logic circuits using Low power Encoder,”2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 142-147, doi: 10.1109/iSES54909.2022.00038.
2021
- S. Gadgil and C. Vudadha, “Design of CNFET-based Low-Power Ternary Sequential Logic circuits,” 2021 IEEE 21st International Conference on Nanotechnology (NANO), 2021, pp. 169-172, doi: 10.1109/NANO51122.2021.9514328.
2020
- H. Sirugudi, S. Gadgil and C. Vudadha, “A Novel Low Power Ternary Multiplier Design using CNFETs,” 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020, pp. 25-30, doi: 10.1109/VLSID49098.2020.00022.
2019
- P. Patel, N. Doddapaneni, S. Gadgil and C. Vudadha, “Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs,” 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019, pp. 280-283, doi: 10.1109/iSES47678.2019.00069.
Areas of Interest:
- Multivalued Logic Circuit design (Ternary circuits)
- CNTFET(Carbon-Nanotube-Field-Effect-Transistor)-based Circuit design
- FPGA-based System design
- Hardware Acceleration using FPGA for Machine Learning Algorithms Implementation
Reviewer of Journal:
- Circuits, Systems and Signal Processing (CSSP) Journal, Springer.
